There is usually provided a thick oxide layer on the field area between semiconductor element regions on a semiconductor integrated circuit device to prevent lack of isolation caused by parasitic effects.
The method of isolating elements using such an oxidation layer is the BOX (Burying Oxide into Silicon Groove) method which is well-known. The BOX Method includes the following steps.
First a resist mask for etching and ion-implantation is provided on a predetermined element region of a semiconductor substrate.
Next, a field area of the substrate is etched to a certain depth and a groove surrounding the predetermined element region is formed. Impurities of the same conductivity type as that of the substrate are introduced into the groove by ion-implantation technique for preventing conductivity type inversion.
After this, an oxidation layer is buried in the groove through a conventional lift-off method. Furthermore, semiconductor elements, for example insulated gate type field effect transistors, are formed on the predetermined element region of the semiconductor substrate. Then metal interconnections are provided between the semiconductor elements.
According to the BOX Method, the size of the element region is defined by the resist mask for etching and ion-implantation which is provided in advance on the semiconductor substrate. Therefore integrated circuit devices made through the BOX Method have less dimension error and meet high integration density. Furthermore, the BOX Method contributes to high lithography accuracy for the wiring process and higher reliability, because the surface of the substrate remains flat.
According to the above BOX Method, the impurities for preventing conductivity type reversion are implanted into the bottom part of the groove formed in the semiconductor substrate but not into the side walls of the groove. Because parasitic channel effects arise often in the side wall part of the groove, it is not always possible to achieve sufficient element isolation.
FIG. 1 shows the relation between the gate voltage Vg and drain current Id of an insulated gate type field effect transistor (IGFET). The sub-threshold characteristic is shown for insulated gate type field effect transistors provided as semiconductor elements. Curve 3 shows a sub-threshold characteristic comprising a portion of an essentially desirable characteristic curve 1 and a portion of the characteristic curve 2 of a parasitic transistor. Such a characteristic causes a leakage current in the off-state of the transistors and is likely to cause operating errors or failure of elements of the integrated circuit.